Speed versus accuracy trade-offs in microarchitectural simulations

Joshua J. Yi, Resit Sendag, David J. Lilja, Douglas M. Hawkins

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


Due to the long simulation time of the reference input set, computer architects often use reduced time simulation techniques to shorten the simulation time. However, what has not yet been thoroughly evaluated is the accuracy of these techniques relative to the reference input set and with respect to each other. To rectify this deficiency, this paper uses three methods to characterize reduced input set, truncated execution, and sampling-based simulation techniques while also examining their speed vs. accuracy trade-off and configuration dependence. Our results show that the three sampling-based techniques, SimPoint, SMARTS, and random sampling, have the best accuracy, the best speed vs. accuracy trade-off, and the least configuration dependence. On the other hand, the reduced input set and truncated execution simulation techniques had generally poor accuracy, were not significantly faster than the sampling-based techniques, and were severely configuration dependent. The final contribution of this paper is a decision tree which can help architects choose the most appropriate technique for their simulations.

Original languageEnglish (US)
Pages (from-to)1549-1563
Number of pages15
JournalIEEE Transactions on Computers
Issue number11
StatePublished - Nov 2007

Bibliographical note

Funding Information:
This work was supported in part by US National Science Foundation Grant CCF-0541162, Intel, and the Minnesota Supercomputing Institute. A preliminary version of this work was first presented at the 11th International Symposium on High-Performance Computer Architecture (HPCA ’05) [21].


  • Measurement techniques
  • Modeling of computer architecture
  • Modeling techniques


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