Speculative register promotion using advanced load address table (ALAT)

Jin Lin, Tong Chen, Wei Chung Hsu, Pen Chung Yew

Research output: Chapter in Book/Report/Conference proceedingConference contribution

27 Scopus citations

Abstract

The pervasive use of pointers with complicated patterns in C programs often constrains compiler alias analysis to yield conservative register allocation and promotion. Speculative register promotion with hardware support has the potential to more aggressively promote memory references into registers in the presence of aliases. This paper studies the use of the advanced load address table (ALAT), a data speculation feature defined in the IA-64 architecture, for speculative register promotion. An algorithm for speculative register promotion based on partial redundancy elimination is presented. The algorithm is implemented in Intel's open research compiler (ORC). Experiments on SPEC CPU2000 benchmark programs are conducted to show that speculative register promotion can improve performance of some benchmarks by 1% to 7%.

Original languageEnglish (US)
Title of host publicationInternational Symposium on Code Generation and Optimization, CGO 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages125-134
Number of pages10
ISBN (Electronic)076951913X, 9780769519135
DOIs
StatePublished - Jan 1 2003
EventInternational Symposium on Code Generation and Optimization, CGO 2003 - San Francisco, United States
Duration: Mar 23 2003Mar 26 2003

Publication series

NameInternational Symposium on Code Generation and Optimization, CGO 2003

Other

OtherInternational Symposium on Code Generation and Optimization, CGO 2003
CountryUnited States
CitySan Francisco
Period3/23/033/26/03

Keywords

  • Computer science
  • Delay
  • Hardware
  • Libraries
  • Optimizing compilers
  • Pattern analysis
  • Program processors
  • Registers
  • Runtime

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