Specific design and optimization of JTAG IP core

Xiaobo Zhang, Yanfeng Jiang, Jiaxin Ju

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A JTAG IP core based on IEEE1149.1 standard has been reported here, including its design and implementation. It has been described using synthesized Verilog HDL language. Simulation demonstration has also been made and the result has been synthesized. It has been demonstrated that the IP core design is feasibility. Moreover, based on the characteristic of DFT using JTAG standard, some improvements on the JTAG structure are proposed to get an optimized result.

Original languageEnglish (US)
Title of host publication2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
DOIs
StatePublished - Sep 17 2009
Event2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09 - Chengdu, China
Duration: Apr 28 2009Apr 29 2009

Publication series

Name2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09

Conference

Conference2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09
CountryChina
CityChengdu
Period4/28/094/29/09

Keywords

  • ATE
  • IEEE 1149.1
  • IP core

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