@inproceedings{d81aceb1668844b498bb60d13a37cbe3,
title = "Specific design and optimization of JTAG IP core",
abstract = "A JTAG IP core based on IEEE1149.1 standard has been reported here, including its design and implementation. It has been described using synthesized Verilog HDL language. Simulation demonstration has also been made and the result has been synthesized. It has been demonstrated that the IP core design is feasibility. Moreover, based on the characteristic of DFT using JTAG standard, some improvements on the JTAG structure are proposed to get an optimized result.",
keywords = "ATE, IEEE 1149.1, IP core",
author = "Xiaobo Zhang and Yanfeng Jiang and Jiaxin Ju",
year = "2009",
month = sep,
day = "17",
doi = "10.1109/CAS-ICTD.2009.4960877",
language = "English (US)",
isbn = "9781424425877",
series = "2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09",
booktitle = "2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09",
note = "2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, ICTD'09 ; Conference date: 28-04-2009 Through 29-04-2009",
}