Sleep transistor sizing and adaptive control for supply noise minimization considering resonance

Jie Gu, Hanyong Eom, John Keane, Chris H. Kim

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

The conventional sleep transistor sizing schemes do not consider the resonant supply noise which represents the worst-case supply disturbance. This paper investigates the impact of sleep transistor sizing on different on-chip noise components and shows that, contrary to the conventional wisdom, a larger sleep transistor is not always favored in term of performance when the resonant supply noise is taken into account. To minimize the worst-case supply noise, an optimal sizing scheme using an explicit noise and impedance model is developed and verified by benchmark circuits. Employing the proposed technique results in a reduction of the worst-case noise by 19%, as well as a saving of standby leakage and area overhead by 60% in comparison with conventional sizing scheme. In order to deal with the sporadic nature of the resonant, we propose an adaptive sleep transistor circuit which adjusts the size of sleep transistor on the fly to remove the DC noise penalty of the fixed sizing scheme. Simulation results on 32-nm CMOS technology are used to demonstrate the functionality and effectiveness of the proposed adaptive sizing circuits.

Original languageEnglish (US)
Article number4801591
Pages (from-to)1203-1211
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume17
Issue number9
DOIs
StatePublished - Sep 1 2009

Keywords

  • Circuit modeling
  • IC design
  • Leakage currents
  • Power supply noise

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