TY - GEN
T1 - Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
AU - Zhang, Tianpei
AU - Sapatnekar, Sachin S
N1 - Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.
PY - 2004
Y1 - 2004
N2 - We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route the signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan's noise metric, and our work shows, for the first time, that this metric shows good fidelity on average. Experimental results on testcases with up to about 10,000 nets point towards an asymptotic run time that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion, or only shield insertion after buffer planning.
AB - We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route the signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan's noise metric, and our work shows, for the first time, that this metric shows good fidelity on average. Experimental results on testcases with up to about 10,000 nets point towards an asymptotic run time that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion, or only shield insertion after buffer planning.
UR - https://www.scopus.com/pages/publications/17644383034
UR - https://www.scopus.com/pages/publications/17644383034#tab=citedBy
U2 - 10.1109/ICCD.2004.1347906
DO - 10.1109/ICCD.2004.1347906
M3 - Conference contribution
AN - SCOPUS:17644383034
SN - 0769522319
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 93
EP - 98
BT - Proceedings - IEEE International Conference on Computer Design
T2 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004
Y2 - 11 October 2004 through 13 October 2004
ER -