Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI interconnect under a higher order AWE model

Keyphrases

• High-order 100%
• Buffer Insertion 100%
• VLSI Interconnects 100%
• Assure 20%
• Optimization Algorithm 20%
• Cost Reduction 20%
• Fourth Order 20%
• Cell Placement 20%
• Routing Tree 20%
• Interconnect Resources 20%
• Weighted Sums 20%

Computer Science

• Buffer Insertion 100%
• Timing Constraint 40%
• Interconnect Resource 20%
• Topology 20%
• Experimental Result 20%
• Resource Constraint 20%
• Optimization Algorithm 20%

Physics

• Topology 100%