Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI interconnect under a higher order AWE model

Research output: Contribution to conferencePaperpeer-review

6 Scopus citations

Abstract

We present a simultaneous Buffer Insertion and Non-Hanan Optimization (BINO) algorithm to improve the performance of VLSI interconnect. This algorithm aims to address the realistic situation where both the interconnect resources and timing constraints are stringent and the wire topology is to be optimized using available spaces for buffer insertions after cell placement. These spaces are fixed relative to the changing routing tree during non-Hanan optimization. The objective here is to minimize weighted sum of wire and buffer cost subject to timing constraints. In BINO, buffer insertion and non-Hanan optimization are conducted simultaneously and iteratively in a greedy fashion till the improvements are exhausted. To assure the accuracy of timing evaluation, the fourth order AWE model is employed. Experimental results on both .18μm IC and MCM technology showed significant cost reductions.

Original languageEnglish (US)
Pages133-138
Number of pages6
DOIs
StatePublished - 1999
EventProceedings of the 1999 International Symposium on Physical Design, ISPD-99 - Monterey, CA, USA
Duration: Apr 12 1999Apr 14 1999

Conference

ConferenceProceedings of the 1999 International Symposium on Physical Design, ISPD-99
CityMonterey, CA, USA
Period4/12/994/14/99

Fingerprint Dive into the research topics of 'Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI interconnect under a higher order AWE model'. Together they form a unique fingerprint.

Cite this