Sign extension reduction by propagated-carry selection

To reduce the area and power consumption in constant coefficient multiplications, the coefficient can be encoded using canonic signed digit (CSD) representation. When the partial product terms are added depending on the nonzero bit positions in the CSD-encoded multiplier, all sign bits are properly extended before the addition takes place. In this paper, to reduce the overhead due to sign extension, a new method is proposed based on the fact that carry propagation in the sign-extension part can be controlled such that a desired input bit can be propagated as a carry. Also, a fixed-width multiplier design method suitable for CSD multiplications is proposed. By combining these two methods, it is shown that significant hardware saving can be achieved.