SiGe MODFETS: Overview and issues for sub-100 nm gate-length scaling

S. J. Koester; K. L. Saenger; J. O. Chu; Q. C. Ouyang; J. A. Ott; S. W. Bedell; D. F. Canaperi; J. A. Tornello; C. V. Jahnes

SiGe MODFETS: Overview and issues for sub-100 nm gate-length scaling

S. J. Koester, K. L. Saenger, J. O. Chu, Q. C. Ouyang, J. A. Ott, S. W. Bedell, D. F. Canaperi, J. A. Tornello, C. V. Jahnes

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

SiGe MODFETs are attractive devices for future rf and mixed-signal communications applications, due to their greatly enhanced mobility compared to Si MOSFETs. However, MODFETs have been slow to keep pace with the tremendous advances in scaling technology that have allowed Si MOSFETs to maintain performance leadership, both for digital and analog applications. In order to fulfill their promise for enhanced performance, MODFETs must also be aggressively scaled. In this paper, we provide a description of recent results on sub-100 nm gate-length Si/Si _0.7Ge _0.3 n-MODFETs, and describe the device design and materials issues for the future scalability of these devices.

Original language	English (US)
Title of host publication	SiGe
Subtitle of host publication	Materials, Processing, and Devices - Proceedings of the First Symposium
Editors	D. Harame, J. Boquet, J. Cressler, D. Houghton, H. Iwai, T.-J. King, G. Masini, J. Murota, K. Rim, B. Tillack
Pages	449-458
Number of pages	10
Volume	7
State	Published - Dec 1 2004
Event	SiGe: Materials, Processing, and Devices - Proceedings of the First Symposium - Honolulu, HI, United States Duration: Oct 3 2004 → Oct 8 2004

Other

Other	SiGe: Materials, Processing, and Devices - Proceedings of the First Symposium
Country/Territory	United States
City	Honolulu, HI
Period	10/3/04 → 10/8/04

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Koester, S. J., Saenger, K. L., Chu, J. O., Ouyang, Q. C., Ott, J. A., Bedell, S. W., Canaperi, D. F., Tornello, J. A., & Jahnes, C. V. (2004). SiGe MODFETS: Overview and issues for sub-100 nm gate-length scaling. In D. Harame, J. Boquet, J. Cressler, D. Houghton, H. Iwai, T.-J. King, G. Masini, J. Murota, K. Rim, & B. Tillack (Eds.), SiGe: Materials, Processing, and Devices - Proceedings of the First Symposium (Vol. 7, pp. 449-458). Article 6.1

SiGe MODFETS: Overview and issues for sub-100 nm gate-length scaling. / Koester, S. J.; Saenger, K. L.; Chu, J. O. et al.
SiGe: Materials, Processing, and Devices - Proceedings of the First Symposium. ed. / D. Harame; J. Boquet; J. Cressler; D. Houghton; H. Iwai; T.-J. King; G. Masini; J. Murota; K. Rim; B. Tillack. Vol. 7 2004. p. 449-458 6.1.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Koester, SJ, Saenger, KL, Chu, JO, Ouyang, QC, Ott, JA, Bedell, SW, Canaperi, DF, Tornello, JA & Jahnes, CV 2004, SiGe MODFETS: Overview and issues for sub-100 nm gate-length scaling. in D Harame, J Boquet, J Cressler, D Houghton, H Iwai, T-J King, G Masini, J Murota, K Rim & B Tillack (eds), SiGe: Materials, Processing, and Devices - Proceedings of the First Symposium. vol. 7, 6.1, pp. 449-458, SiGe: Materials, Processing, and Devices - Proceedings of the First Symposium, Honolulu, HI, United States, 10/3/04.

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ER -

SiGe MODFETS: Overview and issues for sub-100 nm gate-length scaling

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