Serial Adders with Overflow Correction

R. O. Berg; L. L. Kinney

doi:10.1109/T-C.1971.223321

Serial Adders with Overflow Correction

R. O. Berg, L. L. Kinney

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.

Original language	English (US)
Pages (from-to)	668-671
Number of pages	4
Journal	IEEE Transactions on Computers
Volume	C-20
Issue number	6
DOIs	https://doi.org/10.1109/T-C.1971.223321
State	Published - Jun 1971
Externally published	Yes

Keywords

Cascaded adders
overflow detection and correction
parallel processing
serial addition

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10.1109/T-C.1971.223321

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@article{df22475b156e42b8b007653bc0e2705b,

title = "Serial Adders with Overflow Correction",

abstract = "A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.",

keywords = "Cascaded adders, overflow detection and correction, parallel processing, serial addition",

author = "Berg, {R. O.} and Kinney, {L. L.}",

year = "1971",

month = jun,

doi = "10.1109/T-C.1971.223321",

language = "English (US)",

volume = "C-20",

pages = "668--671",

journal = "IEEE Transactions on Computers",

issn = "0018-9340",

publisher = "IEEE Computer Society",

number = "6",

}

TY - JOUR

T1 - Serial Adders with Overflow Correction

AU - Berg, R. O.

AU - Kinney, L. L.

PY - 1971/6

Y1 - 1971/6

N2 - A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.

AB - A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.

KW - Cascaded adders

KW - overflow detection and correction

KW - parallel processing

KW - serial addition

UR - http://www.scopus.com/inward/record.url?scp=0015080195&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0015080195&partnerID=8YFLogxK

U2 - 10.1109/T-C.1971.223321

DO - 10.1109/T-C.1971.223321

M3 - Article

AN - SCOPUS:0015080195

SN - 0018-9340

VL - C-20

SP - 668

EP - 671

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 6

ER -

Serial Adders with Overflow Correction

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