TY - JOUR
T1 - Self-Initializing Memory Elements
AU - Vinnakota, Bapiraju
AU - Harjani, Ramesh
PY - 1995/7
Y1 - 1995/7
N2 - Test generation for sequential circuits is complicated by the fact that the initial internal state of a circuit, after power-up, cannot be predicted. This is commonly referred to as the initializability problem. In this paper, we present a new solution to the initializability problem—self-initializing memory elements (SIME’s). SIME’s are designed to initialize, at power-up, to a known state. The start-up environment of a memory element is analyzed in detail. This analysis is used to design several different types of SIME’s. Each of the designs meet different user requirements. We also discuss the application of SIME’s to the problem of test generation for sequential circuits. SIME’s have distinct advantages over on-chip reset signals. Compared to off-chip reset signals, they offer a different overhead-benefit trade-off. They may also be used in conjunction with other design for test techniques. In short, they provide a designer with additional flexibility during the design process.
AB - Test generation for sequential circuits is complicated by the fact that the initial internal state of a circuit, after power-up, cannot be predicted. This is commonly referred to as the initializability problem. In this paper, we present a new solution to the initializability problem—self-initializing memory elements (SIME’s). SIME’s are designed to initialize, at power-up, to a known state. The start-up environment of a memory element is analyzed in detail. This analysis is used to design several different types of SIME’s. Each of the designs meet different user requirements. We also discuss the application of SIME’s to the problem of test generation for sequential circuits. SIME’s have distinct advantages over on-chip reset signals. Compared to off-chip reset signals, they offer a different overhead-benefit trade-off. They may also be used in conjunction with other design for test techniques. In short, they provide a designer with additional flexibility during the design process.
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U2 - 10.1109/82.401169
DO - 10.1109/82.401169
M3 - Article
AN - SCOPUS:0029341652
SN - 1057-7130
VL - 42
SP - 461
EP - 472
JO - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
JF - IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
IS - 7
ER -