Scheduling strategies for low-energy programmable digit-serial Reed-Solomon codecs

This paper considers two types digit-serial finite field multiplications, and their applications to the design of low-energy high-performance Reed-Solomon codecs in software, based on a digit-serial finite field data path architecture. The salient feature of this digit-serial approach is that only the digit-cells are implemented in hardware, the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations. It is shown that for larger digit-sizes, more than 60% energy reduction and more than one-third energy-delay reduction can be achieved be using these scheduling approaches for the digit-serial data path as compared with that for parallel data path, for 2-error-correcting Reed-Solomon(n, k) codecs over GF(2⁸), where n can range from 5 to 255. When area becomes critical design constraint, smaller digit-sizes must be used. In that case, the energy and energy-delay reduction can be achieved using combined scheduling strategies.