Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Shimeng Yu; Pai Yu Chen; Yu Cao; Lixue Xia; Yu Wang; Huaqiang Wu

doi:10.1109/IEDM.2015.7409718

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Shimeng Yu
, Pai Yu Chen
, Yu Cao
, Lixue Xia
, Yu Wang
, Huaqiang Wu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

189 Scopus citations

Abstract

The crossbar array architecture with resistive synaptic devices is attractive for on-chip implementation of weighted sum and weight update in the neuro-inspired learning algorithms. This paper discusses the design challenges on scaling up the array size due to non-ideal device properties and array parasitics. Circuit-level mitigation strategies have been proposed to minimize the learning accuracy loss in a large array. This paper also discusses the peripheral circuits design considerations for the neuro-inspired architecture. Finally, a circuit-level macro simulator is developed to explore the design trade-offs and evaluate the overhead of the proposed mitigation strategies as well as project the scaling trend of the neuro-inspired architecture.

Original language	English (US)
Title of host publication	2015 IEEE International Electron Devices Meeting, IEDM 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	17.3.1-17.3.4
ISBN (Electronic)	9781467398930
DOIs	https://doi.org/10.1109/IEDM.2015.7409718
State	Published - Feb 16 2015
Externally published	Yes
Event	61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States Duration: Dec 7 2015 → Dec 9 2015

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2016-February
ISSN (Print)	0163-1918

Other

Other	61st IEEE International Electron Devices Meeting, IEDM 2015
Country/Territory	United States
City	Washington
Period	12/7/15 → 12/9/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

crossbar array
machine learning
neuromorphic computing
Resistive memory
synaptic device

Publisher link

10.1109/IEDM.2015.7409718

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Yu, S., Chen, P. Y., Cao, Y., Xia, L., Wang, Y., & Wu, H. (2015). Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect. In 2015 IEEE International Electron Devices Meeting, IEDM 2015 (pp. 17.3.1-17.3.4). Article 7409718 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409718

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect. / Yu, Shimeng; Chen, Pai Yu; Cao, Yu et al.
2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 17.3.1-17.3.4 7409718 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yu, S, Chen, PY, Cao, Y, Xia, L, Wang, Y & Wu, H 2015, Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect. in 2015 IEEE International Electron Devices Meeting, IEDM 2015., 7409718, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2016-February, Institute of Electrical and Electronics Engineers Inc., pp. 17.3.1-17.3.4, 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, United States, 12/7/15. https://doi.org/10.1109/IEDM.2015.7409718

Yu S, Chen PY, Cao Y, Xia L, Wang Y, Wu H. Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect. In 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 17.3.1-17.3.4. 7409718. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2015.7409718

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abstract = "The crossbar array architecture with resistive synaptic devices is attractive for on-chip implementation of weighted sum and weight update in the neuro-inspired learning algorithms. This paper discusses the design challenges on scaling up the array size due to non-ideal device properties and array parasitics. Circuit-level mitigation strategies have been proposed to minimize the learning accuracy loss in a large array. This paper also discusses the peripheral circuits design considerations for the neuro-inspired architecture. Finally, a circuit-level macro simulator is developed to explore the design trade-offs and evaluate the overhead of the proposed mitigation strategies as well as project the scaling trend of the neuro-inspired architecture.",

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Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

Abstract

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Keywords

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