Scalable stochastic processors

Sriram Narayanan, John Sartori, Rakesh Kumar, Douglas L. Jones

Research output: Chapter in Book/Report/Conference proceedingConference contribution

92 Scopus citations


Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive scaling of voltage and frequency, and shrinking design margins. Fortunately, many emerging applications can tolerate computational errors caused by hardware unreliabilities, at least during certain execution intervals. In this paper, we propose scalable stochastic processors, a computing platform for error-tolerant applications that is able to scale gracefully according to performance demands and power constraints while producing outputs that are, in the worst case, stochastically correct. Scalability is achieved by exposing to the application layer multiple functional units that differ in their architecture but share functionality. A mobile video encoding application here is able to achieve the lowest power consumption at any bitrate demand by dynamically switching between functional-unit architectures.

Original languageEnglish (US)
Title of host publicationDATE 10 - Design, Automation and Test in Europe
Number of pages4
StatePublished - Jun 9 2010
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
Duration: Mar 8 2010Mar 12 2010

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591


OtherDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010


Cite this

Narayanan, S., Sartori, J., Kumar, R., & Jones, D. L. (2010). Scalable stochastic processors. In DATE 10 - Design, Automation and Test in Europe (pp. 335-338). [5457181] (Proceedings -Design, Automation and Test in Europe, DATE).