Scalable methods for the analysis and optimization of gate oxide breakdown

Jianxin Fang, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

In this paper we first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to gate oxide breakdown. Our approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 6-11x relaxation of the predicted lifetime with respect to the ultra-pessimistic area-scaling method. Next, we develop a posynomial-based optimization approach to perform gate sizing for oxide reliability in addition to timing and area.

Original languageEnglish (US)
Title of host publicationProceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010
Pages638-645
Number of pages8
DOIs
StatePublished - May 28 2010
Event11th International Symposium on Quality Electronic Design, ISQED 2010 - San Jose, CA, United States
Duration: Mar 22 2010Mar 24 2010

Publication series

NameProceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010

Other

Other11th International Symposium on Quality Electronic Design, ISQED 2010
CountryUnited States
CitySan Jose, CA
Period3/22/103/24/10

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