TY - GEN
T1 - Scalable methods for the analysis and optimization of gate oxide breakdown
AU - Fang, Jianxin
AU - Sapatnekar, Sachin S
PY - 2010/5/28
Y1 - 2010/5/28
N2 - In this paper we first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to gate oxide breakdown. Our approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 6-11x relaxation of the predicted lifetime with respect to the ultra-pessimistic area-scaling method. Next, we develop a posynomial-based optimization approach to perform gate sizing for oxide reliability in addition to timing and area.
AB - In this paper we first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to gate oxide breakdown. Our approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 6-11x relaxation of the predicted lifetime with respect to the ultra-pessimistic area-scaling method. Next, we develop a posynomial-based optimization approach to perform gate sizing for oxide reliability in addition to timing and area.
UR - http://www.scopus.com/inward/record.url?scp=77952596529&partnerID=8YFLogxK
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U2 - 10.1109/ISQED.2010.5450507
DO - 10.1109/ISQED.2010.5450507
M3 - Conference contribution
AN - SCOPUS:77952596529
SN - 9781424464555
T3 - Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010
SP - 638
EP - 645
BT - Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010
T2 - 11th International Symposium on Quality Electronic Design, ISQED 2010
Y2 - 22 March 2010 through 24 March 2010
ER -