Abstract
Gate oxide breakdown is an important reliability issue that has been widely studied at the individual transistor level, but has seen very little work at the circuit level. We first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to this phenomenon. The new approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 4.8-6.2 × relaxation of the predicted lifetime with respect to the pessimistic area-scaling method for nominal process parameters. Next, we extend the failure analysis to include the effect of process variations, and derive that the circuit FP at a specified time instant has a lognormal distribution due to process variations. Circuits with variations show 19%-24% lifetime degradation against nominal analysis and 4.7-5.9 × lifetime relaxation against area-scaling method under variations. Both parts of our work are verified by extensive simulations and proved to be effective, accurate and scalable.
| Original language | English (US) |
|---|---|
| Article number | 6043901 |
| Pages (from-to) | 1960-1973 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 20 |
| Issue number | 11 |
| DOIs | |
| State | Published - 2012 |
Bibliographical note
Funding Information:Manuscript received March 04, 2011; revised June 24, 2011; accepted August 12, 2011. Date of publication October 13, 2011; date of current version July 27, 2012. This work was supported in part by the Semiconductor Research Corporation (SRC) under Contract 2007-TJ-1572 and the National Science Foundation (NSF) under Award CCR-1017778.
Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.
Keywords
- Circuit reliability
- failure analysis
- oxide breakdown
- process variation