Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Keyphrases

• Modularized 100%
• Convolutional Neural Network 100%
• Compiler 66%
• OpenCL 66%
• Convolutional Neural Network Model 66%
• FPGA Resources 66%
• Portable System 33%
• Design Strategy 33%
• Automatically Generate 33%
• Parallelization 33%
• Design Optimization 33%
• Memory Access 33%
• System Architecture 33%
• Resource Constraints 33%
• Quantitatively Analysis 33%
• High-level Synthesis 33%
• Network Parameters 33%
• Scalable Computing 33%
• Level Design 33%
• Neural Network Implementation 33%
• Fast Design 33%
• Acceleration Schemes 33%
• Algorithm Structure 33%
• Compliers 33%
• Level Optimization 33%
• Great Acceleration 33%
• Hardware Level 33%
• Large Data Volumes 33%
• FPGA System 33%
• Altera 33%
• Neural Network Structure 33%
• Deep Learning Algorithm 33%
• AlexNet 33%
• FPGA Acceleration 33%
• High-level Synthesis Tools 33%
• RTL Implementation 33%
• Hardware Acceleration of Deep Learning 33%
• Proposed Methodology 33%
• Fine Levels 33%
• End-to-end Convolutional Neural Network 33%

Computer Science

• Convolutional Neural Network 100%
• Neural Network Model 33%
• High Level Synthesis 33%
• OpenCL 33%
• Deep Learning 33%
• Parallelism 16%
• Design Strategy 16%
• System Architectures 16%
• Synthesis Tool 16%
• Neural Network Architecture 16%
• Memory Access 16%
• Intensive Computation 16%
• Hardware Level 16%
• hardware acceleration 16%
• Resource Constraint 16%
• Design Optimization 16%
• Network Parameter 16%