TY - JOUR
T1 - SAC
T2 - A SYSTOLIC ARRAY CONTROLLER CHIP.
AU - Smith, Ross
AU - Dillon, Mike
AU - Sobelman, Gerald E
PY - 1988
Y1 - 1988
N2 - SAC (systolic array controller) is a chip designed for use with an NCR 16-bit fixed-point multiplier/accumulator (MAC) chip to form a two-chip cell in systolic arrays for signal processing applications. The SAC/MAC cell can be used as an inexpensive, flexible building block for either one-dimensional or two-dimensional systolic arrays in either application-specific or general-purpose machines. The SAC provides an interface to other cells via four parallel ports. It routes data to and from the companion high-speed MAC via one 16-bit bidirectional port, controls the MAC, and provides 64 words of scratchpad memory for programs and data.
AB - SAC (systolic array controller) is a chip designed for use with an NCR 16-bit fixed-point multiplier/accumulator (MAC) chip to form a two-chip cell in systolic arrays for signal processing applications. The SAC/MAC cell can be used as an inexpensive, flexible building block for either one-dimensional or two-dimensional systolic arrays in either application-specific or general-purpose machines. The SAC provides an interface to other cells via four parallel ports. It routes data to and from the companion high-speed MAC via one 16-bit bidirectional port, controls the MAC, and provides 64 words of scratchpad memory for programs and data.
UR - http://www.scopus.com/inward/record.url?scp=0023799423&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0023799423&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0023799423
SN - 0736-7791
SP - 2049
EP - 2052
JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
JF - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
ER -