SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits

Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

A wide variety of error tolerant applications supports the use of approximate circuits that achieve power savings by introducing small errors. This paper proposes a fast and novel algorithm for the design of such circuits with the goal of maximizing power savings, constrained by a fixed error budget, through an analytical expression to optimally select the number of bits to be approximated. This algorithm outperforms uniform approximation schemes by over 30% in power savings, with negligible computational overhead.

Original languageEnglish (US)
Title of host publicationProceedings of the 54th Annual Design Automation Conference 2017, DAC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450349277
DOIs
StatePublished - Jun 18 2017
Event54th Annual Design Automation Conference, DAC 2017 - Austin, United States
Duration: Jun 18 2017Jun 22 2017

Publication series

NameProceedings - Design Automation Conference
VolumePart 128280
ISSN (Print)0738-100X

Other

Other54th Annual Design Automation Conference, DAC 2017
CountryUnited States
CityAustin
Period6/18/176/22/17

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