TY - GEN
T1 - SABER
T2 - 54th Annual Design Automation Conference, DAC 2017
AU - Sengupta, Deepashree
AU - Snigdha, Farhana Sharmin
AU - Hu, Jiang
AU - Sapatnekar, Sachin S
N1 - Publisher Copyright:
© 2017 ACM.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2017/6/18
Y1 - 2017/6/18
N2 - A wide variety of error tolerant applications supports the use of approximate circuits that achieve power savings by introducing small errors. This paper proposes a fast and novel algorithm for the design of such circuits with the goal of maximizing power savings, constrained by a fixed error budget, through an analytical expression to optimally select the number of bits to be approximated. This algorithm outperforms uniform approximation schemes by over 30% in power savings, with negligible computational overhead.
AB - A wide variety of error tolerant applications supports the use of approximate circuits that achieve power savings by introducing small errors. This paper proposes a fast and novel algorithm for the design of such circuits with the goal of maximizing power savings, constrained by a fixed error budget, through an analytical expression to optimally select the number of bits to be approximated. This algorithm outperforms uniform approximation schemes by over 30% in power savings, with negligible computational overhead.
UR - http://www.scopus.com/inward/record.url?scp=85023611925&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85023611925&partnerID=8YFLogxK
U2 - 10.1145/3061639.3062314
DO - 10.1145/3061639.3062314
M3 - Conference contribution
AN - SCOPUS:85023611925
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 18 June 2017 through 22 June 2017
ER -