RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Jordi Cortadella; Marc Galceran-Oms; Mike Kishinevsky; Sachin S. Sapatnekar

doi:10.1109/JPROC.2015.2456189

RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Jordi Cortadella, Marc Galceran-Oms, Mike Kishinevsky, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs.

Original language	English (US)
Article number	7275092
Pages (from-to)	2061-2075
Number of pages	15
Journal	Proceedings of the IEEE
Volume	103
Issue number	11
DOIs	https://doi.org/10.1109/JPROC.2015.2456189
State	Published - Nov 1 2015

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

Design automation
architectural pipelining
high-level synthesis
logic synthesis
timing elasticity

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10.1109/JPROC.2015.2456189

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RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Abstract

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