RTL Synthesis: From Logic Synthesis to Automatic Pipelining

Jordi Cortadella, Marc Galceran-Oms, Mike Kishinevsky, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs.

Original languageEnglish (US)
Article number7275092
Pages (from-to)2061-2075
Number of pages15
JournalProceedings of the IEEE
Issue number11
StatePublished - Nov 1 2015

Bibliographical note

Publisher Copyright:
© 2015 IEEE.


  • Design automation
  • architectural pipelining
  • high-level synthesis
  • logic synthesis
  • timing elasticity


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