The binary number representation has dominated digital logic for decades due to its compact storage requirements. However, since the number system is positional, it needs to “unpack” bits, perform computations, and repack the bits back to binary (e.g., partial products in multiplication). An alternative representation is the unary number system: we use N bits, out of which the first M are 1 and the rest are 0 to represent the value M/N. We present a novel method which first converts binary numbers to unary using thermometer encoders, then uses a “scaling network” followed by voting gates that we call “alternator logic”, followed by an adder tree to convert the numbers back to the binary format. For monotonically increasing functions, the scaling network is all we need, which essentially uses only the routing resources and flip-flops on the FPGA architecture. Our method is especially well-suited to FPGAs due to the abundant availability of routing and FF resources, and for the ability of FPGAs to realize high fanout gates for highly oscillating functions. We compare our method to stochastic computing and to conventional binary implementations on a number of functions, as well as on two common image processing applications. Our method is clearly superior to the conventional binary implementation: our area×delay cost is on average only 3%, 8% and 32% of the binary method for 8-, 10-, and 12-bit resolutions respectively. Compared to stochastic computing, our cost is 6%, 5%, and 8% for those resolutions. The area cost includes conversions from and to the binary format. Our method out performs the conventional binary method on an edge detection algorithm. However, it is not competitive with the binary method on the median filtering application due to the high cost of generating and saving unary representations of the input pixels.