We consider the problem of determining the smallest clock period for a combinational circuit by considering both the long and short paths. To bring in the timing of the circuit, we make use of a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. The bounds on the clock period can alternatively be viewed as optimization objectives. At the physical level, the problem becomes applying transistor sizing and delay buffer insertion to achieve specified upper bounds on clock period and latency. We present experimental results that reflect the complexity of the optimization problem. The clock period determination can also be extended to circuits with feedbacks.