Role of long and short paths in circuit performance optimization

Siu Wing Cheng, Hsi chuan Chen, David H Du

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

We consider the problem of determining the smallest clock period for a combinational circuit by considering both the long and short paths. To bring in the timing of the circuit, we make use of a new class of paths called the shortest destabilizing paths as well as the longest sensitizable paths. The bounds on the clock period can alternatively be viewed as optimization objectives. At the physical level, the problem becomes applying transistor sizing and delay buffer insertion to achieve specified upper bounds on clock period and latency. We present experimental results that reflect the complexity of the optimization problem. The clock period determination can also be extended to circuits with feedbacks.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
PublisherPubl by IEEE
Pages543-548
Number of pages6
ISBN (Print)0818628227
StatePublished - Dec 1 1992
EventProceedings of the 29th ACM/IEEE Design Automation Conference - Anaheim, CA, USA
Duration: Jun 8 1992Jun 12 1992

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0146-7123

Other

OtherProceedings of the 29th ACM/IEEE Design Automation Conference
CityAnaheim, CA, USA
Period6/8/926/12/92

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