Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology

Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

High functional yield is one of the key challenges for subthreshold standard cell designs. Device upsizing is a commonly used but suboptimal method due to its overheads in energy and area. In this paper, we propose a robustness-driven intra-cell mixed-Vt design methodology (MVT-ULV) for the robust ultra-low voltage operation. It uses low threshold voltage transistors in the weak pulling network of logic gates to enhance the robustness. It guarantees the high functional yield with the minimum energy/area overheads. We demonstrate on a commercial 65nm CMOS process that, our proposed design methodology shows up to 60mV and 110mV robustness improvement at 300mV power supply voltage over the commercial library cells and the cells built with previous Leakage-Minimization mixed-Vt methods (MVT-LM) under the same cell area constraints, respectively. In addition, the proposed MVT-ULV library enables ITC'99 benchmark circuits to show on average 30.1% and 78.1% energy-efficiency improvement when compared to the libraries built with the device-upsizing methods and the previous MVT-LM methods under the same yield constraints, respectively.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013
Pages323-328
Number of pages6
DOIs
StatePublished - Dec 11 2013
Event2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013 - Beijing, China
Duration: Sep 4 2013Sep 6 2013

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013
CountryChina
CityBeijing
Period9/4/139/6/13

Keywords

  • Intra-cell mixed-V
  • multi-V design
  • standard cell library
  • subthreshold circuits
  • yield enhancement

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