TY - GEN
T1 - Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology
AU - Zhao, Wenfeng
AU - Ha, Yajun
AU - Hoo, Chin Hau
AU - Alvarez, Anastacia B.
PY - 2013/12/11
Y1 - 2013/12/11
N2 - High functional yield is one of the key challenges for subthreshold standard cell designs. Device upsizing is a commonly used but suboptimal method due to its overheads in energy and area. In this paper, we propose a robustness-driven intra-cell mixed-Vt design methodology (MVT-ULV) for the robust ultra-low voltage operation. It uses low threshold voltage transistors in the weak pulling network of logic gates to enhance the robustness. It guarantees the high functional yield with the minimum energy/area overheads. We demonstrate on a commercial 65nm CMOS process that, our proposed design methodology shows up to 60mV and 110mV robustness improvement at 300mV power supply voltage over the commercial library cells and the cells built with previous Leakage-Minimization mixed-Vt methods (MVT-LM) under the same cell area constraints, respectively. In addition, the proposed MVT-ULV library enables ITC'99 benchmark circuits to show on average 30.1% and 78.1% energy-efficiency improvement when compared to the libraries built with the device-upsizing methods and the previous MVT-LM methods under the same yield constraints, respectively.
AB - High functional yield is one of the key challenges for subthreshold standard cell designs. Device upsizing is a commonly used but suboptimal method due to its overheads in energy and area. In this paper, we propose a robustness-driven intra-cell mixed-Vt design methodology (MVT-ULV) for the robust ultra-low voltage operation. It uses low threshold voltage transistors in the weak pulling network of logic gates to enhance the robustness. It guarantees the high functional yield with the minimum energy/area overheads. We demonstrate on a commercial 65nm CMOS process that, our proposed design methodology shows up to 60mV and 110mV robustness improvement at 300mV power supply voltage over the commercial library cells and the cells built with previous Leakage-Minimization mixed-Vt methods (MVT-LM) under the same cell area constraints, respectively. In addition, the proposed MVT-ULV library enables ITC'99 benchmark circuits to show on average 30.1% and 78.1% energy-efficiency improvement when compared to the libraries built with the device-upsizing methods and the previous MVT-LM methods under the same yield constraints, respectively.
KW - Intra-cell mixed-V
KW - multi-V design
KW - standard cell library
KW - subthreshold circuits
KW - yield enhancement
UR - http://www.scopus.com/inward/record.url?scp=84889610521&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84889610521&partnerID=8YFLogxK
U2 - 10.1109/ISLPED.2013.6629317
DO - 10.1109/ISLPED.2013.6629317
M3 - Conference contribution
AN - SCOPUS:84889610521
SN - 9781479912353
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 323
EP - 328
BT - Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013
T2 - 2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013
Y2 - 4 September 2013 through 6 September 2013
ER -