How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.
|Original language||English (US)|
|Title of host publication||Proceedings - 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016|
|Publisher||IEEE Computer Society|
|Number of pages||8|
|State||Published - Oct 5 2016|
|Event||22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016 - Porto Alegre, Brazil|
Duration: May 8 2016 → May 11 2016
|Name||Proceedings - International Symposium on Asynchronous Circuits and Systems|
|Other||22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016|
|Period||5/8/16 → 5/11/16|
Bibliographical noteFunding Information:
This work has been partially supported by funds from the Spanish Ministry for Economy and Competitiveness and the European Union (FEDER funds) under grant TIN2013-46181-C2-1-R, the Generalitat de Catalunya (2014 SGR 1034 and FI-DGR 2015) and a Fulbright award.
- on-chip variability
- reactive clock
- ring oscillators