Ring oscillator clocks and margins

Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.

Original languageEnglish (US)
Title of host publicationProceedings - 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016
PublisherIEEE Computer Society
Pages19-26
Number of pages8
ISBN (Electronic)9781467390071
DOIs
StatePublished - Oct 5 2016
Event22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016 - Porto Alegre, Brazil
Duration: May 8 2016May 11 2016

Publication series

NameProceedings - International Symposium on Asynchronous Circuits and Systems
Volume2016-October
ISSN (Print)1522-8681

Other

Other22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016
CountryBrazil
CityPorto Alegre
Period5/8/165/11/16

Bibliographical note

Funding Information:
This work has been partially supported by funds from the Spanish Ministry for Economy and Competitiveness and the European Union (FEDER funds) under grant TIN2013-46181-C2-1-R, the Generalitat de Catalunya (2014 SGR 1034 and FI-DGR 2015) and a Fulbright award.

Keywords

  • on-chip variability
  • reactive clock
  • ring oscillators

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