Ring oscillator clocks and margins

Jordi Cortadella; Marc Lupon; Alberto Moreno; Antoni Roca; Sachin S. Sapatnekar

doi:10.1109/ASYNC.2016.14

Ring oscillator clocks and margins

Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Scopus citations

Abstract

How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.

Original language	English (US)
Title of host publication	Proceedings - 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016
Publisher	IEEE Computer Society
Pages	19-26
Number of pages	8
ISBN (Electronic)	9781467390071
DOIs	https://doi.org/10.1109/ASYNC.2016.14
State	Published - Oct 5 2016
Event	22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016 - Porto Alegre, Brazil Duration: May 8 2016 → May 11 2016

Publication series

Name	Proceedings - International Symposium on Asynchronous Circuits and Systems
Volume	2016-October
ISSN (Print)	1522-8681

Other

Other	22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016
Country/Territory	Brazil
City	Porto Alegre
Period	5/8/16 → 5/11/16

Bibliographical note

Funding Information:
This work has been partially supported by funds from the Spanish Ministry for Economy and Competitiveness and the European Union (FEDER funds) under grant TIN2013-46181-C2-1-R, the Generalitat de Catalunya (2014 SGR 1034 and FI-DGR 2015) and a Fulbright award.

Publisher Copyright:
© 2016 IEEE.

Keywords

on-chip variability
reactive clock
ring oscillators

Publisher link

10.1109/ASYNC.2016.14

http://hdl.handle.net/2117/96481

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Cortadella, J., Lupon, M., Moreno, A., Roca, A., & Sapatnekar, S. S. (2016). Ring oscillator clocks and margins. In Proceedings - 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016 (pp. 19-26). [7584887] (Proceedings - International Symposium on Asynchronous Circuits and Systems; Vol. 2016-October). IEEE Computer Society. https://doi.org/10.1109/ASYNC.2016.14

Ring oscillator clocks and margins. / Cortadella, Jordi; Lupon, Marc; Moreno, Alberto et al.
Proceedings - 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016. IEEE Computer Society, 2016. p. 19-26 7584887 (Proceedings - International Symposium on Asynchronous Circuits and Systems; Vol. 2016-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Cortadella, J, Lupon, M, Moreno, A, Roca, A & Sapatnekar, SS 2016, Ring oscillator clocks and margins. in Proceedings - 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016., 7584887, Proceedings - International Symposium on Asynchronous Circuits and Systems, vol. 2016-October, IEEE Computer Society, pp. 19-26, 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, 5/8/16. https://doi.org/10.1109/ASYNC.2016.14

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Ring oscillator clocks and margins

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