Rigorous extraction of process variations for 65-nm CMOS design

Wei Zhao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka, Yu Cao

Research output: Contribution to journalArticlepeer-review

47 Scopus citations

Abstract

Statistical circuit analysis and optimization are critical for robust nanoscale CMOS design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, a rigorous method to extract process variations from in situ IV measurements is present. Transistor statistics are collected from a test chip fabricated in a 65-nm process. Gate length (L), threshold voltage (Vth) and mobility (μ) are recognized as the leading variation sources, due to the tremendous process challenges in lithography, channel doping, and the stress engineering. To decompose these variations, three critical IV points from the cut-off and linear regions are identified. The extracted L, Vth and μ variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, accurate prediction of the change of drive current in all operation regions and process corners is achieved. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis.

Original languageEnglish (US)
Article number4773506
Pages (from-to)196-203
Number of pages8
JournalIEEE Transactions on Semiconductor Manufacturing
Volume22
Issue number1
DOIs
StatePublished - Feb 2009
Externally publishedYes

Bibliographical note

Funding Information:
Manuscript received May 30, 2008; revised October 28, 2008. Current version published February 04, 2009. This work was supported by the Materials, Structure, and Devices Center (MSD) and the Center of Circuits and System Solutions (C2S2), two of five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program, and by an IBM Faculty Award.

Keywords

  • Compact modeling
  • Process variation
  • Spatial correlation
  • Threshold voltage variation

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