Review and comparison of clock jitter noise reduction techniques for lowpass continuous-time delta-sigma modulators

Keyphrases

• Noise Reduction Algorithm 100%
• Clock Jitter 100%
• Continuous-time sigma-delta Modulator 100%
• Jitter Noise 100%
• Jitter Effect 60%
• System Design 20%
• Performance Metrics 20%
• Resistors 20%
• Power Consumption 20%
• Process Variation 20%
• Feedback Technique 20%
• Switched Capacitor 20%
• Single-bit 20%
• Medium Frequency 20%
• Circuit Complexity 20%
• High Sampling Frequency 20%
• Multibit Operation 20%
• Fixed Width 20%

Computer Science

• sigma delta modulator 100%
• Continuous Time 100%
• Power Consumption 50%
• Performance Metric 50%
• Synthesis Technique 50%
• Process Variation 50%
• Extensibility 50%
• Circuit Complexity 50%
• system level design 50%
• Sampling Frequency 50%

Engineering

• Continuous Time 100%
• Electric Power Utilization 50%
• Metrics 50%
• Sampling Frequency 50%
• Switched Capacitor 50%
• Single Bit 50%
• Detailed Review 50%
• Extensibility 50%
• Pulse Duration 50%
• Process Variation 50%