Reliability Characterization of Logic-Compatible NAND Flash Memory based Synapses with 3-bit per Cell Weights and 1μA Current Steps

Minsu Kim, Jeehwan Song, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A logic-compatible embedded NAND (eNAND) flash memory based synapse with 3 bit per cell weight storage and 1μA current steps was demonstrated in a standard 65nm CMOS process. The eNAND flash based neuromorphic core consists of 16stack eNAND strings. Each flash cell is composed of 3 transistors (2 PMOS and 1 NMOS) and each string is connected to the main bitline via 2 additional NMOS access transistors. In this work, we realized 3 bit weight based on 1μA current steps using the proposed back-pattern tolerant program-verify scheme. To evaluate the reliability of eNAND Flash based synapses, we measured the temperature dependence, read disturbance, and retention characteristics from a 65nm test chip with 3 bit per cell weight storage and 1μA current steps.

Original languageEnglish (US)
Title of host publication2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728131993
DOIs
StatePublished - Apr 2020
Event2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Virtual, Online, United States
Duration: Apr 28 2020May 30 2020

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
Volume2020-April
ISSN (Print)1541-7026

Conference

Conference2020 IEEE International Reliability Physics Symposium, IRPS 2020
CountryUnited States
CityVirtual, Online
Period4/28/205/30/20

Keywords

  • Embedded NAND (eNAND)
  • logic-compatible NAND flash memory
  • neuromorphic computing
  • read disturbance
  • retention characteristic

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