Abstract
A logic-compatible embedded NAND (eNAND) flash memory based synapse with 3 bit per cell weight storage and 1μA current steps was demonstrated in a standard 65nm CMOS process. The eNAND flash based neuromorphic core consists of 16stack eNAND strings. Each flash cell is composed of 3 transistors (2 PMOS and 1 NMOS) and each string is connected to the main bitline via 2 additional NMOS access transistors. In this work, we realized 3 bit weight based on 1μA current steps using the proposed back-pattern tolerant program-verify scheme. To evaluate the reliability of eNAND Flash based synapses, we measured the temperature dependence, read disturbance, and retention characteristics from a 65nm test chip with 3 bit per cell weight storage and 1μA current steps.
| Original language | English (US) |
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| Title of host publication | 2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728131993 |
| DOIs | |
| State | Published - Apr 2020 |
| Event | 2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Virtual, Online, United States Duration: Apr 28 2020 → May 30 2020 |
Publication series
| Name | IEEE International Reliability Physics Symposium Proceedings |
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| Volume | 2020-April |
| ISSN (Print) | 1541-7026 |
Conference
| Conference | 2020 IEEE International Reliability Physics Symposium, IRPS 2020 |
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| Country/Territory | United States |
| City | Virtual, Online |
| Period | 4/28/20 → 5/30/20 |
Bibliographical note
Publisher Copyright:© 2020 IEEE.
Keywords
- Embedded NAND (eNAND)
- logic-compatible NAND flash memory
- neuromorphic computing
- read disturbance
- retention characteristic