Reliability Analysis of a Delay-Locked Loop under HCI and BTI Degradation

Tonmoy Dhar; Sachin S. Sapatnekar

doi:10.1109/IRPS.2019.8720447

Reliability Analysis of a Delay-Locked Loop under HCI and BTI Degradation

Tonmoy Dhar, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper studies the impact of hot carrier injection and bias temperature instability on a mixed-signal delay locked loop, at the block and system levels. Aging affects delays on the reset line of the phase detector, degrading sensitivity to input phase differences. Aging also increases threshold voltage mismatch in the charge pump, causing the control voltage of the voltage-controlled delay line to drift, reducing the acquisition time. The delay range of the voltage-controlled delay line also shifts due to aging. Numerical results on a 45nm CMOS process are presented.

Original language	English (US)
Title of host publication	2019 IEEE International Reliability Physics Symposium, IRPS 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538695043
DOIs	https://doi.org/10.1109/IRPS.2019.8720447
State	Published - May 22 2019
Event	2019 IEEE International Reliability Physics Symposium, IRPS 2019 - Monterey, United States Duration: Mar 31 2019 → Apr 4 2019

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
Volume	2019-March
ISSN (Print)	1541-7026

Conference

Conference	2019 IEEE International Reliability Physics Symposium, IRPS 2019
Country/Territory	United States
City	Monterey
Period	3/31/19 → 4/4/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

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10.1109/IRPS.2019.8720447

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Dhar, T., & Sapatnekar, S. S. (2019). Reliability Analysis of a Delay-Locked Loop under HCI and BTI Degradation. In 2019 IEEE International Reliability Physics Symposium, IRPS 2019 Article 8720447 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2019-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2019.8720447

Reliability Analysis of a Delay-Locked Loop under HCI and BTI Degradation. / Dhar, Tonmoy; Sapatnekar, Sachin S.
2019 IEEE International Reliability Physics Symposium, IRPS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8720447 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2019-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dhar, T & Sapatnekar, SS 2019, Reliability Analysis of a Delay-Locked Loop under HCI and BTI Degradation. in 2019 IEEE International Reliability Physics Symposium, IRPS 2019., 8720447, IEEE International Reliability Physics Symposium Proceedings, vol. 2019-March, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Reliability Physics Symposium, IRPS 2019, Monterey, United States, 3/31/19. https://doi.org/10.1109/IRPS.2019.8720447

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AB - This paper studies the impact of hot carrier injection and bias temperature instability on a mixed-signal delay locked loop, at the block and system levels. Aging affects delays on the reset line of the phase detector, degrading sensitivity to input phase differences. Aging also increases threshold voltage mismatch in the charge pump, causing the control voltage of the voltage-controlled delay line to drift, reducing the acquisition time. The delay range of the voltage-controlled delay line also shifts due to aging. Numerical results on a 45nm CMOS process are presented.

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Reliability Analysis of a Delay-Locked Loop under HCI and BTI Degradation

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