Reliability Analysis of a Delay-Locked Loop under HCI and BTI Degradation

Tonmoy Dhar, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper studies the impact of hot carrier injection and bias temperature instability on a mixed-signal delay locked loop, at the block and system levels. Aging affects delays on the reset line of the phase detector, degrading sensitivity to input phase differences. Aging also increases threshold voltage mismatch in the charge pump, causing the control voltage of the voltage-controlled delay line to drift, reducing the acquisition time. The delay range of the voltage-controlled delay line also shifts due to aging. Numerical results on a 45nm CMOS process are presented.

Original languageEnglish (US)
Title of host publication2019 IEEE International Reliability Physics Symposium, IRPS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538695043
DOIs
StatePublished - May 22 2019
Event2019 IEEE International Reliability Physics Symposium, IRPS 2019 - Monterey, United States
Duration: Mar 31 2019Apr 4 2019

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
Volume2019-March
ISSN (Print)1541-7026

Conference

Conference2019 IEEE International Reliability Physics Symposium, IRPS 2019
CountryUnited States
CityMonterey
Period3/31/194/4/19

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Dhar, T., & Sapatnekar, S. S. (2019). Reliability Analysis of a Delay-Locked Loop under HCI and BTI Degradation. In 2019 IEEE International Reliability Physics Symposium, IRPS 2019 [8720447] (IEEE International Reliability Physics Symposium Proceedings; Vol. 2019-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2019.8720447