### Abstract

The author addresses register minimization in design of digital signal processing (DSP) data format converter architectures. Systematic lifetime analysis is used to calculate the minimum number of registers needed for any arbitrarily specified data format converter. The minimum number of registers can be used to design a data format converter architecture using a novel forward-backward register allocation scheme. The number of registers needed in the scheme is about half of that needed in the forward register allocation scheme. Examples of converters presented include matrix transposers, and general (m, d_{1}) → (n, d_{2}) data format converters. The (m, d_{1}) → (n, d_{2}) converter inputs m words and d_{1} bits per word in one input cycle and outputs n words and d_{2} bits per word in one output cycle (d_{1} and d_{2} lie between 1 and the word-length w).

Original language | English (US) |
---|---|

Pages (from-to) | 2367-2370 |

Number of pages | 4 |

Journal | Proceedings - IEEE International Symposium on Circuits and Systems |

Volume | 4 |

State | Published - Dec 1 1991 |

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### Cite this

**Register minimization in DSP data format converters.** / Parhi, Keshab K.

Research output: Contribution to journal › Article

*Proceedings - IEEE International Symposium on Circuits and Systems*, vol. 4, pp. 2367-2370.

}

TY - JOUR

T1 - Register minimization in DSP data format converters

AU - Parhi, Keshab K

PY - 1991/12/1

Y1 - 1991/12/1

N2 - The author addresses register minimization in design of digital signal processing (DSP) data format converter architectures. Systematic lifetime analysis is used to calculate the minimum number of registers needed for any arbitrarily specified data format converter. The minimum number of registers can be used to design a data format converter architecture using a novel forward-backward register allocation scheme. The number of registers needed in the scheme is about half of that needed in the forward register allocation scheme. Examples of converters presented include matrix transposers, and general (m, d1) → (n, d2) data format converters. The (m, d1) → (n, d2) converter inputs m words and d1 bits per word in one input cycle and outputs n words and d2 bits per word in one output cycle (d1 and d2 lie between 1 and the word-length w).

AB - The author addresses register minimization in design of digital signal processing (DSP) data format converter architectures. Systematic lifetime analysis is used to calculate the minimum number of registers needed for any arbitrarily specified data format converter. The minimum number of registers can be used to design a data format converter architecture using a novel forward-backward register allocation scheme. The number of registers needed in the scheme is about half of that needed in the forward register allocation scheme. Examples of converters presented include matrix transposers, and general (m, d1) → (n, d2) data format converters. The (m, d1) → (n, d2) converter inputs m words and d1 bits per word in one input cycle and outputs n words and d2 bits per word in one output cycle (d1 and d2 lie between 1 and the word-length w).

UR - http://www.scopus.com/inward/record.url?scp=0026304984&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026304984&partnerID=8YFLogxK

M3 - Article

VL - 4

SP - 2367

EP - 2370

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

SN - 0271-4310

ER -