Register minimization in DSP data format converters

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Abstract

The author addresses register minimization in design of digital signal processing (DSP) data format converter architectures. Systematic lifetime analysis is used to calculate the minimum number of registers needed for any arbitrarily specified data format converter. The minimum number of registers can be used to design a data format converter architecture using a novel forward-backward register allocation scheme. The number of registers needed in the scheme is about half of that needed in the forward register allocation scheme. Examples of converters presented include matrix transposers, and general (m, d1) → (n, d2) data format converters. The (m, d1) → (n, d2) converter inputs m words and d1 bits per word in one input cycle and outputs n words and d2 bits per word in one output cycle (d1 and d2 lie between 1 and the word-length w).

Original languageEnglish (US)
Pages (from-to)2367-2370
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - Dec 1 1991

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Digital signal processing

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Register minimization in DSP data format converters. / Parhi, Keshab K.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, 01.12.1991, p. 2367-2370.

Research output: Contribution to journalArticle

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