Abstract
The author addresses register minimization in design of digital signal processing (DSP) data format converter architectures. Systematic lifetime analysis is used to calculate the minimum number of registers needed for any arbitrarily specified data format converter. The minimum number of registers can be used to design a data format converter architecture using a novel forward-backward register allocation scheme. The number of registers needed in the scheme is about half of that needed in the forward register allocation scheme. Examples of converters presented include matrix transposers, and general (m, d1) → (n, d2) data format converters. The (m, d1) → (n, d2) converter inputs m words and d1 bits per word in one input cycle and outputs n words and d2 bits per word in one output cycle (d1 and d2 lie between 1 and the word-length w).
| Original language | English (US) |
|---|---|
| Pages (from-to) | 2367-2370 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| State | Published - Dec 1 1991 |
| Event | 1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore Duration: Jun 11 1991 → Jun 14 1991 |