Register minimization in cost-optimal synthesis of DSP architectures

Kazuhito Ito, Keshab K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

In this paper we propose a generalized technique to count the number of registers supporting overlapped scheduling and a general digit-serial data format. This technique is integrated into an integer linear programming model which minimizes the cost of registers as well as the cost of processors and data format converters to synthesize a cost-optimal architecture for a given digital signal processing algorithm. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to up to 12.8% savings in the total cost of the synthesized architecture when compared with synthesis performed without including the register cost in the total cost.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on VLSI Signal Processing, Proceedings
PublisherIEEE
Pages207-216
Number of pages10
StatePublished - Dec 1 1995
EventProceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn
Duration: Oct 16 1995Oct 18 1995

Other

OtherProceedings of the 1995 IEEE Workshop on VLSI Signal Processing
CityOsaka, Jpn
Period10/16/9510/18/95

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