Reducing the signal Electromigration effects on different logic gates by cell layout optimization

Gracieli Posser, Lucas De Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In modern integrated circuits, the Electromigration (EM) effects are not just seen on power delivery networks. EM is also an increasing problem in the internal metal wires of cells, referred as cell-internal signal Electromigration. In this work we present a detailed analysis of the cell-internal signal Electromigration effects considering different logic gates. The lifetime optimization by placing the output pin of the gates is dependent of the output wire shape and the logic of the gate. We are also presenting ways to improve the lifetime of the cells optimizing the cell layout.

Original languageEnglish (US)
Title of host publication2015 IEEE 6th Latin American Symposium on Circuits and Systems, LASCAS 2015 - Conference Proceedings
EditorsFernando Silveira, Lorena Garcia, Alfredo Arnaud
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479983322
DOIs
StatePublished - Sep 9 2015
Event6th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2015 - Montevideo, Uruguay
Duration: Feb 24 2015Feb 27 2015

Publication series

Name2015 IEEE 6th Latin American Symposium on Circuits and Systems, LASCAS 2015 - Conference Proceedings

Other

Other6th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2015
CountryUruguay
CityMontevideo
Period2/24/152/27/15

Keywords

  • Electromigration
  • Logic Gates
  • Physical Design
  • Signal Wires
  • cell-internal signal electromigration

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