@inproceedings{363e58d2334141ca9b9a74bcf169a12f,
title = "Reducing the signal Electromigration effects on different logic gates by cell layout optimization",
abstract = "In modern integrated circuits, the Electromigration (EM) effects are not just seen on power delivery networks. EM is also an increasing problem in the internal metal wires of cells, referred as cell-internal signal Electromigration. In this work we present a detailed analysis of the cell-internal signal Electromigration effects considering different logic gates. The lifetime optimization by placing the output pin of the gates is dependent of the output wire shape and the logic of the gate. We are also presenting ways to improve the lifetime of the cells optimizing the cell layout.",
keywords = "Electromigration, Logic Gates, Physical Design, Signal Wires, cell-internal signal electromigration",
author = "Gracieli Posser and {De Paris}, Lucas and Vivek Mishra and Palkesh Jain and Ricardo Reis and Sapatnekar, {Sachin S}",
year = "2015",
month = sep,
day = "9",
doi = "10.1109/LASCAS.2015.7250429",
language = "English (US)",
series = "2015 IEEE 6th Latin American Symposium on Circuits and Systems, LASCAS 2015 - Conference Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Fernando Silveira and Lorena Garcia and Alfredo Arnaud",
booktitle = "2015 IEEE 6th Latin American Symposium on Circuits and Systems, LASCAS 2015 - Conference Proceedings",
note = "6th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2015 ; Conference date: 24-02-2015 Through 27-02-2015",
}