In this paper, we address the problem of performance oriented synthesis of pass transistor logic (PTL) circuits using a binary decision diagram (BDD) decomposition technique. We transform the BDD decomposition problem into a recursive bipartitioning problem and solve the latter using a max-flow min-cut technique. We use the area and delay cost of the PTL implementation of the logic function to guide the bipartitioning scheme. Using recursive bipartitioning and a one-hot multiplexer circuit, we show that our PTL implementation has logarithmic delay in the number of inputs, under certain assumptions. The experimental results on benchmark circuits are promising, since they show the significant delay reductions with small or no area overheads as compared to previous approaches.
|Number of pages
|IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
|Published - Jan 1 2001
|International Conference on Computer-Aided Design 2001 - San Jose, CA, United States
Duration: Nov 4 2001 → Nov 8 2001