Recovery-driven design: A power minimization methodology for error-tolerant processor modules

Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori

Research output: Chapter in Book/Report/Conference proceedingConference contribution

56 Scopus citations


Conventional CAD methodologies optimize a processor module for correct operation, and prohibit timing violations during nominal operation. In this paper, we propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of correct operation. We show that significant power benefits are possible from a recovery-driven design flow that deliberately allows errors caused by voltage overscaling ([10],[3]) to occur during nominal operation, while relying on an error recovery technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target error rate. We demonstrate power benefits of up to 25%, 19%, 22%, 24%, 20%, 28%, and 20% versus traditional P&R at error rates of 0.125%, 0.25%, 0.5%, 1%, 2%, 4%, and 8%, respectively. Coupling recovery-driven design with an error recovery technique enables increased efficiency and additional power savings.

Original languageEnglish (US)
Title of host publicationProceedings of the 47th Design Automation Conference, DAC '10
Number of pages6
StatePublished - 2010
Event47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
Duration: Jun 13 2010Jun 18 2010

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other47th Design Automation Conference, DAC '10
Country/TerritoryUnited States
CityAnaheim, CA


  • Power minimization
  • Recovery-driven design


Dive into the research topics of 'Recovery-driven design: A power minimization methodology for error-tolerant processor modules'. Together they form a unique fingerprint.

Cite this