RECONFIGURABLE VARISTRUCTURE ARRAY PROCESSOR.

G. Jack Lipovski, Anand Tripathi

Research output: Contribution to conferencePaperpeer-review

24 Scopus citations

Abstract

Description of a multiprocessing system using conventional microprocessors which are dynamically restructured to get the desired word width and dynamically reconfigured to obtain the desired memory height. The system is space shared so that several tasks concurrently execute in different blocks of the partitioned resources, and communication is provided between and within task blocks. The dynamic reconfiguration and restructuring of the different processors and memory modules and interprocessor and I/O communications are achieved using an interconnection network called an SW-banyan, the cost of which is proportional to n Ln n, where n is the number of modules to be interconnected. A great deal of flexibility and power is available by means of an inexpensive SW-banyan switching network.

Original languageEnglish (US)
Pages165-174
Number of pages10
StatePublished - Jan 1 2017
EventProc of the Int Conf on Parallel Process - Bellaire, Mich
Duration: Aug 23 1977Aug 26 1977

Other

OtherProc of the Int Conf on Parallel Process
CityBellaire, Mich
Period8/23/778/26/77

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