The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits to work with conservative clock frequencies. Various schemes for clock generation based on ring oscillators and adaptive clocks have been proposed with the goal to mitigate the power and performance losses attributable to variability. However, there has been no systematic analysis to quantify the benefits of such schemes and no signoff method has been proposed for timing correctness. This paper presents and analyzes a Reactive Clocking scheme with Variability-Tracking Jitter (RClk) that uses variability as an opportunity to reduce power by continuously adjusting the clock frequency to the varying environmental conditions, and thus, reduces guardband margins significantly. Power can be reduced between 20% and 40% at iso-performance and performance can be boosted by similar amounts at iso-power. Additionally, energy savings can be translated to substantial advantages in terms of reliability and thermal management. More importantly, the technology can be adopted with minimal modifications to conventional EDA flows.
|Original language||English (US)|
|Title of host publication||Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||8|
|State||Published - Dec 14 2015|
|Event||33rd IEEE International Conference on Computer Design, ICCD 2015 - New York City, United States|
Duration: Oct 18 2015 → Oct 21 2015
|Name||Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015|
|Other||33rd IEEE International Conference on Computer Design, ICCD 2015|
|City||New York City|
|Period||10/18/15 → 10/21/15|
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