Radix 2 shared division/square root algorithm and its VLSI architecture

Hosahalli R. Srinivas, Keshab K Parhi

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper presents the VLSI architecture of a shared division/square root operator that operates on the mantissas (23-b in length) of single precision IEEE 754 1985 std., floating point numbers. The division and square root algorithms used in this operator are based on radix 2 signed digit representations and operate in a digit-by-digit manner. These two algorithms perform quotient and root digit selection using two most-significant digits of the partial remainder. Previously proposed shared division square-root algorithms required more than two most-significant digits of the partial remainder to be observed during quotient or root digit selection. Lower the number of digits observed for quotient or root digit selection, faster the operation. Due to this, the algorithms proposed in this scheme are faster than previous schemes. This architecture has been layed out using 1.2 micron 5.0 V CMOS 2 metal process and requires 14.82 mm2 area.

Original languageEnglish (US)
Pages (from-to)37-60
Number of pages24
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume21
Issue number1
DOIs
StatePublished - Jan 1 1999

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VLSI Architecture
Digit
Square root
Division
Quotient
Roots
Remainder
Mathematical operators
Partial
Metals
Floating point
Operator
Signed

Cite this

Radix 2 shared division/square root algorithm and its VLSI architecture. / Srinivas, Hosahalli R.; Parhi, Keshab K.

In: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 21, No. 1, 01.01.1999, p. 37-60.

Research output: Contribution to journalArticle

@article{9293854209264dafb2907ece7b01c04b,
title = "Radix 2 shared division/square root algorithm and its VLSI architecture",
abstract = "This paper presents the VLSI architecture of a shared division/square root operator that operates on the mantissas (23-b in length) of single precision IEEE 754 1985 std., floating point numbers. The division and square root algorithms used in this operator are based on radix 2 signed digit representations and operate in a digit-by-digit manner. These two algorithms perform quotient and root digit selection using two most-significant digits of the partial remainder. Previously proposed shared division square-root algorithms required more than two most-significant digits of the partial remainder to be observed during quotient or root digit selection. Lower the number of digits observed for quotient or root digit selection, faster the operation. Due to this, the algorithms proposed in this scheme are faster than previous schemes. This architecture has been layed out using 1.2 micron 5.0 V CMOS 2 metal process and requires 14.82 mm2 area.",
author = "Srinivas, {Hosahalli R.} and Parhi, {Keshab K}",
year = "1999",
month = "1",
day = "1",
doi = "10.1023/A:1008075621962",
language = "English (US)",
volume = "21",
pages = "37--60",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer New York",
number = "1",

}

TY - JOUR

T1 - Radix 2 shared division/square root algorithm and its VLSI architecture

AU - Srinivas, Hosahalli R.

AU - Parhi, Keshab K

PY - 1999/1/1

Y1 - 1999/1/1

N2 - This paper presents the VLSI architecture of a shared division/square root operator that operates on the mantissas (23-b in length) of single precision IEEE 754 1985 std., floating point numbers. The division and square root algorithms used in this operator are based on radix 2 signed digit representations and operate in a digit-by-digit manner. These two algorithms perform quotient and root digit selection using two most-significant digits of the partial remainder. Previously proposed shared division square-root algorithms required more than two most-significant digits of the partial remainder to be observed during quotient or root digit selection. Lower the number of digits observed for quotient or root digit selection, faster the operation. Due to this, the algorithms proposed in this scheme are faster than previous schemes. This architecture has been layed out using 1.2 micron 5.0 V CMOS 2 metal process and requires 14.82 mm2 area.

AB - This paper presents the VLSI architecture of a shared division/square root operator that operates on the mantissas (23-b in length) of single precision IEEE 754 1985 std., floating point numbers. The division and square root algorithms used in this operator are based on radix 2 signed digit representations and operate in a digit-by-digit manner. These two algorithms perform quotient and root digit selection using two most-significant digits of the partial remainder. Previously proposed shared division square-root algorithms required more than two most-significant digits of the partial remainder to be observed during quotient or root digit selection. Lower the number of digits observed for quotient or root digit selection, faster the operation. Due to this, the algorithms proposed in this scheme are faster than previous schemes. This architecture has been layed out using 1.2 micron 5.0 V CMOS 2 metal process and requires 14.82 mm2 area.

UR - http://www.scopus.com/inward/record.url?scp=0032647088&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032647088&partnerID=8YFLogxK

U2 - 10.1023/A:1008075621962

DO - 10.1023/A:1008075621962

M3 - Article

VL - 21

SP - 37

EP - 60

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 1

ER -