PVT-aware leakage reduction for on-die caches with improved read stability

Keyphrases

• Caching 100%
• On-die 100%
• Leakage Reduction 100%
• Read Stability 100%
• Leakage Reduction Techniques 100%
• Sleep Mode 100%
• High Temperature 50%
• Circuit Techniques 50%
• Measurement Results 50%
• Temperature Fluctuation 50%
• Leakage Saving 50%
• Performance Penalty 50%
• SRAM Cache 50%
• Cell Leakage 50%
• Overhead Energy 50%
• SRAM Cell 50%
• Pulse Period 50%
• Fast Processes 50%
• Static Noise Margin 50%
• Simple Circuit 50%
• Access Behavior 50%
• Process Fluctuation 50%
• SRAM Array 50%
• Leakage Condition 50%
• Self-decay 50%
• Memory Cell 50%

Engineering

• Sleep Mode 100%
• Energy Engineering 50%
• Temperature Fluctuation 50%
• Simple Circuit 50%
• Pulse Period 50%
• Performance Penalty 50%
• Noise Margin 50%