PVT-aware leakage reduction for on-die caches with improved read stability

Chris H. Kim, Jae Joon Kim, Ik Joon Chang, K. Roy

Research output: Contribution to journalArticlepeer-review

26 Scopus citations

Abstract

Effectiveness of previous SRAM leakage reduction techniques vary significantly as the leakage variation gets worse with process and temperature fluctuation. This paper proposes a simple circuit technique that adaptively trades off overhead energy for maximum leakage savings under severe leakage variations. The proposed run-time leakage reduction technique for on-die SRAM caches considers architectural access behavior to determine how often the SRAM blocks should enter a sleep mode. A self-decay circuit generates a periodic sleep pulse with an adaptive pulse period, which puts the SRAM array into a sleep mode more frequently at high leakage conditions (fast process, high temperature) and vice versa. An 0.18-/spl mu/m 1.8-V 16-kbyte SRAM testchip shows 94.2% reduction in SRAM cell leakage at a performance penalty less than 2%. Measurement results also indicate that our proposed memory cell improves SRAM static noise margin by 25%.

Original languageEnglish (US)
Pages (from-to)170-178
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number1
DOIs
StatePublished - Jan 2006

Bibliographical note

Funding Information:
Manuscript received April 2, 2005; revised May 27, 2005. This work was supported in part by the DARPA PAC/C program and the Semiconductor Research Corporation, and in part through the Intel Ph.D. fellowship program. C. H. Kim is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: chriskim@ece.umn.edu). J.-J. Kim is with the VLSI Design Department, IBM T.J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: jjkim2@us.ibm.com). I.-J. Chang and K. Roy are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 USA (e-mail: ichang@ecn.purdue.edu; kaushik@ecn.purdue.edu). Digital Object Identifier 10.1109/JSSC.2005.859315

Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.

Keywords

  • Architectural access behavior
  • Maximum leakage savings
  • On-die SRAM caches
  • Overhead energy
  • PVT-aware leakage reduction
  • Periodic sleep pulse
  • Read stability improvement
  • Run-time leakage reduction technique
  • Self-decay circuit
  • Sleep mode

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