PVT-aware leakage reduction for on-die caches with improved read stability

Chris H. Kim; Jae Joon Kim; Ik Joon Chang; K. Roy

doi:10.1109/JSSC.2005.859315

PVT-aware leakage reduction for on-die caches with improved read stability

Chris H. Kim, Jae Joon Kim, Ik Joon Chang, K. Roy

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

30 Scopus citations

Abstract

Effectiveness of previous SRAM leakage reduction techniques vary significantly as the leakage variation gets worse with process and temperature fluctuation. This paper proposes a simple circuit technique that adaptively trades off overhead energy for maximum leakage savings under severe leakage variations. The proposed run-time leakage reduction technique for on-die SRAM caches considers architectural access behavior to determine how often the SRAM blocks should enter a sleep mode. A self-decay circuit generates a periodic sleep pulse with an adaptive pulse period, which puts the SRAM array into a sleep mode more frequently at high leakage conditions (fast process, high temperature) and vice versa. An 0.18-/spl mu/m 1.8-V 16-kbyte SRAM testchip shows 94.2% reduction in SRAM cell leakage at a performance penalty less than 2%. Measurement results also indicate that our proposed memory cell improves SRAM static noise margin by 25%.

Original language	English (US)
Pages (from-to)	170-178
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	41
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2005.859315
State	Published - Jan 2006

Bibliographical note

Funding Information:
Manuscript received April 2, 2005; revised May 27, 2005. This work was supported in part by the DARPA PAC/C program and the Semiconductor Research Corporation, and in part through the Intel Ph.D. fellowship program. C. H. Kim is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: [email protected]). J.-J. Kim is with the VLSI Design Department, IBM T.J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]). I.-J. Chang and K. Roy are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/JSSC.2005.859315

Keywords

Architectural access behavior
Maximum leakage savings
On-die SRAM caches
Overhead energy
PVT-aware leakage reduction
Periodic sleep pulse
Read stability improvement
Run-time leakage reduction technique
Self-decay circuit
Sleep mode

Publisher link

10.1109/JSSC.2005.859315

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abstract = "Effectiveness of previous SRAM leakage reduction techniques vary significantly as the leakage variation gets worse with process and temperature fluctuation. This paper proposes a simple circuit technique that adaptively trades off overhead energy for maximum leakage savings under severe leakage variations. The proposed run-time leakage reduction technique for on-die SRAM caches considers architectural access behavior to determine how often the SRAM blocks should enter a sleep mode. A self-decay circuit generates a periodic sleep pulse with an adaptive pulse period, which puts the SRAM array into a sleep mode more frequently at high leakage conditions (fast process, high temperature) and vice versa. An 0.18-/spl mu/m 1.8-V 16-kbyte SRAM testchip shows 94.2\% reduction in SRAM cell leakage at a performance penalty less than 2\%. Measurement results also indicate that our proposed memory cell improves SRAM static noise margin by 25\%.",

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note = "Funding Information: Manuscript received April 2, 2005; revised May 27, 2005. This work was supported in part by the DARPA PAC/C program and the Semiconductor Research Corporation, and in part through the Intel Ph.D. fellowship program. C. H. Kim is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: [email protected]). J.-J. Kim is with the VLSI Design Department, IBM T.J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]). I.-J. Chang and K. Roy are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/JSSC.2005.859315",

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PVT-aware leakage reduction for on-die caches with improved read stability

Abstract

Bibliographical note

Keywords

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