Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS

Sanggeun Lee, Ramesh Harjani, Taehyoun Oh

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

A 6 Gbps frequency-locked loop (FLL) for reference-less clock recovery loop has been designed. Based on the analyzed noise characteristic of the pseudo reference clock and the effect on the FLL output, we propose design strategies to decide the speed of the pseudo clock and the loop bandwidth for low phase noise. A non-linear digital sub loop enables the FLL to converge to the optimal noise bandwidth with a fast lock time. The proto-type reference-less clock recovery loop has been fabricated in 65 nm CMOS process and the FLL occupies 0.131 mm2 chip area. The FLL consumes 12.5 mW from 1 V supply and the measured output jitter is 4.13 ps,rms at 6 GHz.

Original languageEnglish (US)
Pages (from-to)2096-2100
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume69
Issue number4
DOIs
StatePublished - Apr 1 2022

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

  • CMOS
  • FD
  • FLL
  • integrated circuit
  • loop bandwidth
  • phase noise
  • pseudo reference
  • reference-less CDR

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