TY - GEN
T1 - Protecting DSP circuits through obfuscation
AU - Lao, Yingjie
AU - Parhi, Keshab K.
PY - 2014/1/1
Y1 - 2014/1/1
N2 - This paper presents a novel approach to protect digital signal processing (DSP) circuits through obfuscation by using high-level transformations. The goal is to design DSP circuits that are harder to reverse engineer. High-level transformations of iterative data-flow graphs have been exploited for area-speed-power tradeoffs. This is the first attempt to develop a design flow to apply high-level transformations that not only meet these tradeoffs but also simultaneously obfuscate the architectures both structurally and functionally. Several modes of operations are introduced for obfuscation where the outputs are either meaningful from a signal processing point of view, but functionally incorrect, or non-meaningful. Experimental results show that the proposed methodology only introduces relatively small overhead, while a high level of obfuscation is achieved. For instance, the area overhead for a (3l)th-order IIR filter benchmark is only 17.7% with a 128-bit configuration key.
AB - This paper presents a novel approach to protect digital signal processing (DSP) circuits through obfuscation by using high-level transformations. The goal is to design DSP circuits that are harder to reverse engineer. High-level transformations of iterative data-flow graphs have been exploited for area-speed-power tradeoffs. This is the first attempt to develop a design flow to apply high-level transformations that not only meet these tradeoffs but also simultaneously obfuscate the architectures both structurally and functionally. Several modes of operations are introduced for obfuscation where the outputs are either meaningful from a signal processing point of view, but functionally incorrect, or non-meaningful. Experimental results show that the proposed methodology only introduces relatively small overhead, while a high level of obfuscation is achieved. For instance, the area overhead for a (3l)th-order IIR filter benchmark is only 17.7% with a 128-bit configuration key.
UR - http://www.scopus.com/inward/record.url?scp=84907418356&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS.2014.6865256
DO - 10.1109/ISCAS.2014.6865256
M3 - Conference contribution
AN - SCOPUS:84907418356
SN - 9781479934324
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 798
EP - 801
BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Y2 - 1 June 2014 through 5 June 2014
ER -