Process scalability of pulse-based circuits for analog image convolution

Robert D'Angelo, Xiaocong Du, Christopher D. Salthouse, Brent Hollosi, Geremy Freifeld, Wes Uy, Haiyao Huang, Nhut Tran, Armand Chery, Jae Sun Seo, Yu Cao, Dorothy C. Poppe, Sameer R. Sonkusale

Research output: Contribution to journalArticlepeer-review


This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transistor-level simulations. Next, the design of a 180-nm PFM chip with programmable weights is presented, and full image convolutions are demonstrated with the analog hardware. Preliminary chip measurements for a 45-nm implementation are also included to demonstrate process scalability. Design considerations for porting this architecture to nanometer processes, including FinFET technologies, are then discussed. This paper concludes with a simulation study on scaling down to 10 nm using a predictive technology model.

Original languageEnglish (US)
Article number8341826
Pages (from-to)2929-2938
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number9
StatePublished - Sep 2018
Externally publishedYes

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  • Time-mode circuits
  • convolution
  • neuromorphic circuits
  • spiking neurons


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