Electrolyte-gated transistors (EGTs) based on poly(3-hexylthiophene) (P3HT) offer low voltage operation, high transconductance, good operational stability, and low contact resistance. These characteristics derive from the massive electrochemical or double layer capacitance (∼10-100 μF/cm2) of the electrolyte layer that serves as the gate dielectric. However, electric double layer (EDL) formation at the source/electrolyte and drain/electrolyte interfaces results in significant parasitic capacitance in EGTs which degrades dynamic switching performance. Parasitic capacitance in EGTs is reduced by covering the top surfaces of the source/drain electrodes with a low-ĸ dielectric (∼0.6 nF/cm2). The low-ĸ dielectric blocks EDL formation on the electrode surfaces that are in direct contact with the gate electrolyte, reducing the parasitic capacitance by a factor of 104 and providing a route to printed P3HT EGTs on plastic operating at switching frequencies exceeding 10 kHz with 1 V supply voltages.