Abstract
Electrolyte-gated transistors (EGTs) based on poly(3-hexylthiophene) (P3HT) offer low voltage operation, high transconductance, good operational stability, and low contact resistance. These characteristics derive from the massive electrochemical or double layer capacitance (∼10-100 μF/cm2) of the electrolyte layer that serves as the gate dielectric. However, electric double layer (EDL) formation at the source/electrolyte and drain/electrolyte interfaces results in significant parasitic capacitance in EGTs which degrades dynamic switching performance. Parasitic capacitance in EGTs is reduced by covering the top surfaces of the source/drain electrodes with a low-ĸ dielectric (∼0.6 nF/cm2). The low-ĸ dielectric blocks EDL formation on the electrode surfaces that are in direct contact with the gate electrolyte, reducing the parasitic capacitance by a factor of 104 and providing a route to printed P3HT EGTs on plastic operating at switching frequencies exceeding 10 kHz with 1 V supply voltages.
| Original language | English (US) |
|---|---|
| Article number | 053301 |
| Journal | Applied Physics Letters |
| Volume | 113 |
| Issue number | 5 |
| DOIs | |
| State | Published - Jul 30 2018 |
Bibliographical note
Funding Information:We thank the Multi-University Research Initiative (MURI) program (N00014-11-1-0690) sponsored by the Office of Naval Research for financial support. C.D.F. also thanks the NSF (CCF 1408123) for support. Parts of this work were performed at the Characterization Facility and the Nano-Fabrication Center of the University of Minnesota which receive partial support from the NSF. The authors thank S. Brett Walker and Jennifer A. Lewis for Ag reactive ink preparation. F.Z. thanks Ankit Mahajan for initial discussions, Krystopher Jochem for experimental help, and Boxin Tang for ion gel preparation.
Publisher Copyright:
© 2018 Author(s).