Practical strategies for power-efficient computing technologies

Leland Chang, David J. Frank, Robert K. Montoye, Steven J. Koester, Brian L. Ji, Paul W. Coteus, Robert H. Dennard, Wilfried Haensch

Research output: Contribution to journalArticlepeer-review

144 Scopus citations

Abstract

After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $\sim\!\hbox{8}\times$ improvement in power efficiency can be attained without system performance loss in parallelizable applicationsthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

Original languageEnglish (US)
Article number5395765
Pages (from-to)215-236
Number of pages22
JournalProceedings of the IEEE
Volume98
Issue number2
DOIs
StatePublished - Feb 2010

Bibliographical note

Funding Information:
Manuscript received August 27, 2009; accepted October 8, 2009. Current version published January 20, 2010. This work was partially supported by DARPA funding under the STEEP program (AFRL contract FA8650-08-C-7806). L. Chang, D. J. Frank, R. K. Montoye, S. J. Koester, P. W. Coteus, R. H. Dennard, and W. Haensch are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: lelandc@us.ibm.com; djf@us.ibm.com; montoye@us.ibm.com; skoester@us.ibm.com; coteus@us.ibm.com; dennard@us.ibm.com; whaensch@us.ibm.com). B. L. Ji was with IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. He is now at 205 Windsor Rd, Fishkill, NY 12524 USA (e-mail: ji2020@gmail.com).

Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.

Keywords

  • CMOS digital integrated circuits
  • CMOSFETs
  • Circuit optimization
  • Integrated circuit design
  • Integrated circuit interconnections
  • Parallel machines
  • Power distribution

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