Abstract
A new approach for fast retiming of level-clocked circuits is presented here. The method relies on the relation between clock skew and retiming, and computes the optimal skew solution to translate it to a retiming. Since clock skew optimization operates on the latches (rather than the gates as in conventional retiming), it is much faster because of a smaller problem size; the translation to the retiming solution is computationally cheap. The minimum period retiming for each of the ISCAS89 circuits was obtained within minutes by this algorithm.
| Original language | English (US) |
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| Title of host publication | VLSI in Computers and Processors |
| Editors | Anon |
| Publisher | IEEE |
| Pages | 440-445 |
| Number of pages | 6 |
| State | Published - Dec 1 1996 |
| Event | Proceedings of the 1996 International Conference on Computer Design, ICCD'96 - Austin, TX, USA Duration: Oct 7 1996 → Oct 9 1996 |
Other
| Other | Proceedings of the 1996 International Conference on Computer Design, ICCD'96 |
|---|---|
| City | Austin, TX, USA |
| Period | 10/7/96 → 10/9/96 |