Practical algorithm for retiming level-clocked circuits

Naresh Maheshwari, Sachin S. Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

A new approach for fast retiming of level-clocked circuits is presented here. The method relies on the relation between clock skew and retiming, and computes the optimal skew solution to translate it to a retiming. Since clock skew optimization operates on the latches (rather than the gates as in conventional retiming), it is much faster because of a smaller problem size; the translation to the retiming solution is computationally cheap. The minimum period retiming for each of the ISCAS89 circuits was obtained within minutes by this algorithm.

Original languageEnglish (US)
Title of host publicationVLSI in Computers and Processors
Editors Anon
PublisherIEEE
Pages440-445
Number of pages6
StatePublished - Dec 1 1996
EventProceedings of the 1996 International Conference on Computer Design, ICCD'96 - Austin, TX, USA
Duration: Oct 7 1996Oct 9 1996

Other

OtherProceedings of the 1996 International Conference on Computer Design, ICCD'96
CityAustin, TX, USA
Period10/7/9610/9/96

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