Power vs. delay in gate sizing: Conflicting objectives?

Sachin S. Sapatnekar, Weitong Chuang

Research output: Contribution to journalConference articlepeer-review

24 Scopus citations

Abstract

The problem of sizing gates for power-delay tradeoffs is of great interest to designers. In this work, the theoretical basis for gate sizing under delay and power considerations is presented, and results on a practical implementation are presented. The dynamic power as well as the short-circuit power are modeled, using notions of delay and transition density, and the optimization problem is formulated using notions of convex programming. Previous approaches have not modeled the short circuit power, and our experimental results show that the incorporation of this leads to counter-intuitive results where the minimum-power circuit is not necessarily the minimum-sized circuit.

Original languageEnglish (US)
Pages (from-to)463-466
Number of pages4
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
StatePublished - Dec 1 1995
EventProceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: Nov 5 1995Nov 9 1995

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