Power factor correction circuit for faster dynamics and zero steady state error using dual voltage controllers

This paper analyzes dual voltage controllers for single-phase Power Factor Correction Circuits which use boost topology. The slower voltage controller with a low bandwidth operates during the steady state condition, keeping the THD within the required limits and maintaining the de-bus voltage at its reference value. The faster voltage controller with high bandwidth operates only during disturbances. Faster response to disturbances necessitates less energy storage in the dc-bus capacitor, hence a smaller capacitance value resulting in a compact and a light-weight circuit. The comparative study between the proposed scheme and the conventional PFC circuit is carried out. The experimental results for the proposed model are presented.