Power factor correction circuit for faster dynamics and zero steady state error using dual voltage controllers

Nitin Bhiwapurkar, Manoj Rathi, Ned Mohan

Research output: Contribution to conferencePaper

1 Scopus citations

Abstract

This paper analyzes dual voltage controllers for single-phase Power Factor Correction Circuits which use boost topology. The slower voltage controller with a low bandwidth operates during the steady state condition, keeping the THD within the required limits and maintaining the de-bus voltage at its reference value. The faster voltage controller with high bandwidth operates only during disturbances. Faster response to disturbances necessitates less energy storage in the dc-bus capacitor, hence a smaller capacitance value resulting in a compact and a light-weight circuit. The comparative study between the proposed scheme and the conventional PFC circuit is carried out. The experimental results for the proposed model are presented.

Original languageEnglish (US)
Pages204-208
Number of pages5
DOIs
StatePublished - 2002
EventProceedings of the 2002 28th Annual Conference of the IEEE Industrial Electronics Society - Sevilla, Spain
Duration: Nov 5 2002Nov 8 2002

Other

OtherProceedings of the 2002 28th Annual Conference of the IEEE Industrial Electronics Society
CountrySpain
CitySevilla
Period11/5/0211/8/02

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    Bhiwapurkar, N., Rathi, M., & Mohan, N. (2002). Power factor correction circuit for faster dynamics and zero steady state error using dual voltage controllers. 204-208. Paper presented at Proceedings of the 2002 28th Annual Conference of the IEEE Industrial Electronics Society, Sevilla, Spain. https://doi.org/10.1109/IECON.2002.1187507