The Hierarchical Energy Analysis Tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out.
Bibliographical noteFunding Information:
This work was done while Janardhan H. Satyanarayana was at the University of Minnesota. The research was supported by the Office of Naval Research under contract N00014-91-J-1008 and by Bell Laboratories. We thank Leilei Song,