Power Estimation of Digital Data Paths Using HEAT

Janardhan H. Satyanarayana; Keshab K. Parhi

doi:10.1109/54.844339

Power Estimation of Digital Data Paths Using HEAT

Janardhan H. Satyanarayana, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

The Hierarchical Energy Analysis Tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out.

Original language	English (US)
Pages (from-to)	101-110
Number of pages	10
Journal	IEEE Design and Test of Computers
Volume	17
Issue number	2
DOIs	https://doi.org/10.1109/54.844339
State	Published - Apr 2000

Bibliographical note

Funding Information:
This work was done while Janardhan H. Satyanarayana was at the University of Minnesota. The research was supported by the Office of Naval Research under contract N00014-91-J-1008 and by Bell Laboratories. We thank Leilei Song,

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title = "Power Estimation of Digital Data Paths Using HEAT",

abstract = "The Hierarchical Energy Analysis Tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out.",

author = "Satyanarayana, {Janardhan H.} and Parhi, {Keshab K.}",

note = "Funding Information: This work was done while Janardhan H. Satyanarayana was at the University of Minnesota. The research was supported by the Office of Naval Research under contract N00014-91-J-1008 and by Bell Laboratories. We thank Leilei Song,",

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Power Estimation of Digital Data Paths Using HEAT

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