Power Estimation of Digital Data Paths Using HEAT

Janardhan H. Satyanarayana, Keshab K Parhi

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

The Hierarchical Energy Analysis Tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out.

Original languageEnglish (US)
Pages (from-to)101-110
Number of pages10
JournalIEEE Design and Test of Computers
Volume17
Issue number2
DOIs
StatePublished - Apr 1 2000

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Electric power utilization

Cite this

Power Estimation of Digital Data Paths Using HEAT. / Satyanarayana, Janardhan H.; Parhi, Keshab K.

In: IEEE Design and Test of Computers, Vol. 17, No. 2, 01.04.2000, p. 101-110.

Research output: Contribution to journalArticle

Satyanarayana, Janardhan H. ; Parhi, Keshab K. / Power Estimation of Digital Data Paths Using HEAT. In: IEEE Design and Test of Computers. 2000 ; Vol. 17, No. 2. pp. 101-110.
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