Power Estimation of Digital Data Paths Using HEAT

Janardhan H. Satyanarayana, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

The Hierarchical Energy Analysis Tool lets designers quickly estimate power consumption of various data-path architectures, enabling a power consumption comparison at a high level before the layout design is carried out.

Original languageEnglish (US)
Pages (from-to)101-110
Number of pages10
JournalIEEE Design and Test of Computers
Volume17
Issue number2
DOIs
StatePublished - Apr 2000

Bibliographical note

Funding Information:
This work was done while Janardhan H. Satyanarayana was at the University of Minnesota. The research was supported by the Office of Naval Research under contract N00014-91-J-1008 and by Bell Laboratories. We thank Leilei Song,

Fingerprint Dive into the research topics of 'Power Estimation of Digital Data Paths Using HEAT'. Together they form a unique fingerprint.

Cite this