Power-efficient VLSI implementation of a feature extraction engine for spike sorting in neural recording and signal processing

This paper presents a power-efficient VLSI implementation of a feature extraction engine for the applications of real-time spike sorting. Traditional method like principal components analysis (PCA) works in a batch mode by diagonalizing the covariance matrix constructed from the whole bunch of input data, which is computationally prohibitive and does not favor real-time processing. The proposed hardware framework does not require large volumes of memories by incrementally adjusting the number of estimated principal components in an automatic fashion. Low-voltage circuit design technique has been introduced to achieve significant power saving. The VLSI implementation of the system has a peak power dissipation of 8.59 μW with a 0.5 V supply voltage, and occupies an area of 0.268 mm².