Polysynchronous stochastic circuits

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Clock distribution networks (CDNs) are costly in high-performance ASICs. This paper proposes a new approach: splitting clock domains at a very fine level, down to the level of a handful of gates. Each domain is synchronized with an inexpensive clock signal, generated locally. This is possible by adopting the paradigm of stochastic computation, where signal values are encoded as random bit streams. The design method is illustrated with the synthesis of circuits for applications in signal and image processing.

Original languageEnglish (US)
Title of host publication2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages492-498
Number of pages7
ISBN (Electronic)9781467395694
DOIs
StatePublished - Mar 7 2016
Event21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao
Duration: Jan 25 2016Jan 28 2016

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume25-28-January-2016

Other

Other21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
CountryMacao
CityMacao
Period1/25/161/28/16

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