TY - GEN
T1 - Polysynchronous stochastic circuits
AU - Najafi, M. Hassan
AU - Lilja, David J.
AU - Riedel, Marc
AU - Bazargan, Kia
PY - 2016/3/7
Y1 - 2016/3/7
N2 - Clock distribution networks (CDNs) are costly in high-performance ASICs. This paper proposes a new approach: splitting clock domains at a very fine level, down to the level of a handful of gates. Each domain is synchronized with an inexpensive clock signal, generated locally. This is possible by adopting the paradigm of stochastic computation, where signal values are encoded as random bit streams. The design method is illustrated with the synthesis of circuits for applications in signal and image processing.
AB - Clock distribution networks (CDNs) are costly in high-performance ASICs. This paper proposes a new approach: splitting clock domains at a very fine level, down to the level of a handful of gates. Each domain is synchronized with an inexpensive clock signal, generated locally. This is possible by adopting the paradigm of stochastic computation, where signal values are encoded as random bit streams. The design method is illustrated with the synthesis of circuits for applications in signal and image processing.
UR - http://www.scopus.com/inward/record.url?scp=84996720578&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84996720578&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2016.7428060
DO - 10.1109/ASPDAC.2016.7428060
M3 - Conference contribution
AN - SCOPUS:84996720578
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 492
EP - 498
BT - 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Y2 - 25 January 2016 through 28 January 2016
ER -