Clock distribution networks (CDNs) are costly in high-performance ASICs. This paper proposes a new approach: splitting clock domains at a very fine level, down to the level of a handful of gates. Each domain is synchronized with an inexpensive clock signal, generated locally. This is possible by adopting the paradigm of stochastic computation, where signal values are encoded as random bit streams. The design method is illustrated with the synthesis of circuits for applications in signal and image processing.
|Original language||English (US)|
|Title of host publication||2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||7|
|State||Published - Mar 7 2016|
|Event||21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao|
Duration: Jan 25 2016 → Jan 28 2016
|Name||Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC|
|Other||21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016|
|Period||1/25/16 → 1/28/16|
Bibliographical noteFunding Information:
This work was supported in part by National Science Foundation grant no. CCF-1408123.
© 2016 IEEE.