Polysynchronous clocking: Exploiting the skew tolerance of stochastic circuits

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Abstract

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

Original languageEnglish (US)
Article number7911306
Pages (from-to)1734-1746
Number of pages13
JournalIEEE Transactions on Computers
Volume66
Issue number10
DOIs
StatePublished - Oct 1 2017

Bibliographical note

Funding Information:
This work was supported in part by National Science Foundation grant no. CCF-1408123. Any opinions, findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the NSF. A perliminary version of this paper appeared as [31].

Keywords

  • Polysynchronous clocking
  • clock distribution networks
  • multi-clock circuits
  • relaxed clocking
  • stochastic computing

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